A widely utilized DRAM (Dynamic Random Access Memory) manufacturing process utilizes CMOS (Complementary Metal Oxide Semiconductor) technology to produce DRAM circuits, which comprise an array of unit memory cells, each including one capacitor and one transistor, such as a field effect transistor. In the most common circuit designs, one side of the transistor is connected to one side of the capacitor, the other side of the transistor and the transistor gate are connected to external circuit lines called the digit line and the word line, and the other side of the capacitor is connected to a reference voltage. In such memory cells, an electrical signal charge is stored in a storage node of the capacitor connected to the transistor that charges and discharges the circuit lines of the capacitor.
Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. In pursuit of increased miniaturization, DRAM chips have been continually redesigned to achieve ever higher degrees of integration. However, as the dimensions of the DRAM chips are reduced, the occupation area of each unit memory cell of the DRAM chips must be reduced. This reduction in occupied area necessarily results in a reduction of the dimensions of the capacitor, which, in turn, makes it difficult to ensure required storage capacitance for transmitting a desired signal without malfunction. However, the ability to densely pack the unit memory cells, while maintaining required capacitance levels, results in the necessity to build taller or deeper capacitors in order to maintain adequate charge storage for adequate data retention. Accordingly, taller or deeper capacitors results in aspect ratios that require expensive processes and result in increased opportunities for defects.
Specialized fabrication processes unique to the formation of large aspect ratio devices such as capacitors do not lend themselves to being integrated with logic devices such as controllers or processors. Therefore, it would be advantageous to develop a data storage cell capable of high-density fabrication while not utilizing overly peculiar processing steps that are incompatible with logic device fabrication techniques.